Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
70
4.3.10.
Serial Chip Select Format Register: SCSFR2-0
The serial chip select format register (SCSFR2-0) is used to select an active level of chip select for each
serial chip select, invert the serial clock, configure settings for connection with SPI, and set data direction
and data length of serial data output.
SCSFR1n-0n(n=0 to 11) :Address Base addr + 16
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
CS2
CSLVL
CS2
SCINV
CS2
SPI
CS2
BDS
CS2
L3
CS2
L2
CS2
L1
CS2
L0
1
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
CS1
CSLVL
CS1
SCINV
CS1
SPI
CS1
BDS
CS1
L3
CS1
L2
CS1
L1
CS1
L0
1
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15] CS2CSLVL: Serial chip select level setting bit for chip select 2
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to select the level when the serial
chip select pin 2 is inactive.
CS2CSLVL
Serial chip select pin 2
Serial chip select setting bit
0
Inactive level set to "L"
1
Inactive level set to "H"
Notes:
⋅
This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
⋅
In the slave mode (SCR:MS="0"), setting this bit has no effect.
⋅
When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit14] CS2SCINV: Serial clock invert bit for chip select 2
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to set the serial clock format
when the serial chip select pin 2 is active.
When this bit is set to "0":
⋅
Serial clock output mark level is set to "H".
⋅
Transmission data is output in synchronization with a falling edge of the serial clock in the normal
transfer while it is output in synchronization with a rising edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a rising edge of the serial clock in the normal transfer while it is sampled at
a falling edge of the serial clock in the SPI transfer.
When this bit is set to "1":
⋅
Serial clock output mark level is set to "L".
⋅
Transmission data is output in synchronization with a rising edge of the serial clock in the normal
transfer while it is output in synchronization with a falling edge of the serial clock in the SPI transfer.
⋅
Reception data is sampled at a falling edge of the serial clock in the normal transfer while it is sampled at
a rising edge of the serial clock in the SPI transfer.
MB91520 Series
MN705-00010-1v0-E
1383