Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
82
4.4.1.
Serial Control Register: SCR
The serial control register (SCR) allows you to disable/enable transmission/reception interrupts,
disable/enable transmission idle interrupts, and disable/enable transmissions and receptions. This register
also has setups for generating LIN break field and resetting LIN interface reset (v2.1).
SCRn(n=0 to 11) : Address Base addr + 00
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
bit
UPCL
MS
LBR
RIE
TIE
TBIE
RXE
TXE
0
0
0
0
0
0
0
0
Initial value
R0,W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
Bit name
Function
bit7 UPCL:
Programmable clear bit
This bit initializes the internal state of LIN interface (v2.1).
When this bit is set to "1":
⋅
Directly reset LIN interface (v2.1) (software reset). In this case, the
register settings will be maintained. Note that any active transmission or
reception will be cut off immediately.
⋅
Baud rate generator restarts by reloading the setting value of the BGR
register.
⋅
All transmission and reception and status interrupt sources (SSR:TDRE,
TBI, RDRF, FRE, ORE, LBD, TINT, and SFD) are initialized.
⋅
When this bit is set to "0": No effect.
For reading, "0" is always read out.
Notes:
⋅
Execute a programmable clear after disabling interrupts.
⋅
When using FIFO, disable FIFO (SCR0:FE2,FE1=0) before you execute
a programmable clear
bit6 MS:
Master/slave select bit
This bit selects master or slave mode.
"0" is set: Master mode will be set.
"1" is set: Slave mode will be set.
bit5 LBR:
LIN break field setting bit
(Functions only in the
master operation)
When you write "1" to this bit, the LIN break field and the LIN Break
delimiter with the length specified by the ESCR:LBL1/0 bits and
ESCR:DEL1/0 are generated.
Write:
Writing "0": No effect.
Writing "1": Generates LIN break field.
For reading, "0" will be always read out.
Notes:
⋅
Functions only in the master operation (MS="0").
⋅
Do not set this bit to "1" while LIN break field is being generated.
bit4 RIE:
Reception interrupt enable
bit
⋅
This bit enables or disables the output of reception interrupt request to
the CPU.
⋅
When the RIE bit and reception data flag bit (SSR:RDRF) are set to "1",
or any of the error flag bits (SSR: FRE, ORE) is set to "1", a reception
interrupt request will be output.
bit3 TIE:
Transmission interrupt
enable bit
⋅
This bit enables or disables the output of transmission interrupt request to
the CPU.
⋅
When the TIE bit and the SSR:TDRE are set to "1", a transmission
interrupt request will be output.
MB91520 Series
MN705-00010-1v0-E
1395