Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

[bit8] TINT: Timer interrupt flag

When the serial timer register (STMR) matches the serial timer compare register (STMCR), the serial timer

When this bit is set to "1" and the timer interrupt enable bit (TINTE) is set to "1", a status interrupt request

will be output.

Writing "0" to this bit will reset it to "0".

Writing "1" to this bit has no effect.

TINT

Description

No timer interrupt request

Timer interrupt request

Notes:

⋅

When software reset is triggered (SCR:UPCL="1"), this bit will be reset to "0".

⋅

For read-modify-write instructions, "1" will be read.

⋅

When the synchronous transmission enable bit (TSYNE) is set to "1", this bit will not be set to "1".

[bit7] TINTE: Timer interrupt enable bit

This bit is used to enable/disable timer interrupts to the CPU.

When this bit is set to "1" and the timer interrupt flag (TINT) is set to "1", a status interrupt request will be

output.

TINTE

Description

Interrupts by the serial timer disabled

Interrupts by the serial timer enabled

[bit6] TSYNE: Synchronous transmission enable bit

This bit is used to enable or disable synchronous transmission.

When this bit is set to "1", transmission will be activated if the serial timer register (STMR) matches the

serial timer compare register (STMCR).

TSYNE

Description

Synchronous transmission disabled

The serial timer will be used as a timer.

Synchronous transmission enabled

The serial timer will not be used as a timer.

Notes:

⋅

This bit can be changed only when the serial timer enable bit (TMRE) is set to "0".

⋅

When synchronous transmission is enabled (TSYNE="1") and transmission is disabled (SCR:TXE="0"),

transmission will not be activated, even if the serial timer register (STMR) matches the serial timer

compare register (STMCR).

MB91520 Series

MN705-00010-1v0-E

1405