Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
96
4.4.7.
Serial Timer Compare Register: STMCR
The serial timer compare register (STMCR) is used to set compared values of the serial timer.
STMCRn(n=0 to 11) : Address Base addr + 0C
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15 to bit0] TC15-0: Compare bits
These bits are used to set compared values of the serial timer.
These bits will be compared with the serial timer register (STMR), and when these bits match the value of
the serial timer register immediately after the serial timer register (STMR) is updated, they will set the serial
timer register to "0". Then, if synchronous transmission is disabled (SACSR:TSYNE="0"), these bits will
set the timer interrupt flag (SACSR:INT) to "1", and if synchronous transmission is enabled
(SACSR:TSYNE="1"), these bits will activate transmission.
Notes:
⋅
When (0000)H is set to this register, the serial timer register will remain set to "0".
⋅
When "0000"H is set to this register with synchronous transmission disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division value of the timer operating clock
(SACSR:TDIV) is set to "0000"b during timer operation.
⋅
If transmission data exists (SSR:TDRE="0") with synchronous transmission enabled
(SACSR:TSYNE="1"), an external trigger enabled (SACSR:TRGE="1"), (0000)H set to this register,
and transmission enabled (SCR:TXE="1"), transmission will be started immediately after an edge of an
external trigger set by the trigger select bits (SACSR:TRG1, 0) is detected.
⋅
This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
⋅
If all the following conditions are satisfied, the serial timer register (STMR) might be reset to (0000) H
before baud rate adjustment is made. Therefore, when the automatic baud rate adjustment bit
(SACSR:AUTE) is set to "1", set a larger value to these bits than the value set by the Sync Field upper
limit bit (SFUR).
⋅
The automatic baud rate adjustment bit (SACSR:AUTE) is set to "1"
⋅
These bits have a smaller value than the value set by the Sync Field upper limit bit (SFUR)
MB91520 Series
MN705-00010-1v0-E
1409