Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
106
4.4.13.
LIN Assist Mode Interrupt Enable Register:
LAMIER
LIN assist mode interrupt enable register (LAMIER) enables/disables those interrupts of LIN checksum
error, LIN ID parity error, LIN Sync Data error, LIN ID parity error, LIN bus error, LIN checksum
operation completion, and LIN automatic header completion,
LAMIERn(n=0 to 11) : Address Base addr + 1A
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
-
LCSERIE LPTERIE LSFERIE LBSERIE LCSCIE
-
LAHCIE
0
0
0
0
0
0
0
0
Initial value
R0,W0
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
Attribute
[bit7] Reserved bit
This bit is a reserved bit. The read value is "0". Be sure to write "0" to this bit.
[bit6] LCSERIE: LIN checksum error interrupt enable bit
This bit enables/disables the LIN checksum error interrupt request output to the CPU.
When the LCSERIE bit and the LAMESR:LCSER bits are set to "1", the reception interrupt request is
outputted.
LCSERIE
LIN checksum error interrupt enable bit
0
Disable
1
Enable
[bit5] LPTERIE: LIN ID parity error interrupt enable bit
This bit enables/disables the LIN ID parity error interrupt request output to the CPU.
When the LPTERIE bit and the LAMESR:LPTER bits are set to "1", the reception interrupt request is
outputted.
LPTERIE
LIN parity error interrupt enable bit
0
Disable
1
Enable
[bit4] LSFERIE: LIN Sync Data error interrupt enable bit
This bit enables/disables the LIN Sync Data error interrupt request output to the CPU.
When the LSFERIE bit and the LAHESR:LSFER bits are set to "1", the reception interrupt demand is
outputted.
LSFERIE
LIN Sync Data error interrupt enable bit
0
Disable
1
Enable
MB91520 Series
MN705-00010-1v0-E
1419