Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
108
4.4.14.
LIN Assist Mode Transmission/Reception ID
Register: LAMTID / LAMRID
LIN assist mode transmission/reception ID register (LAMTID/LAMRID) sets a value of the transmission
LIN ID, indicates a parity value of the received LIN ID, and indicates a value of the received LIN ID.
LIN Assist Mode Transmission ID Register (LAMTID)
• LAMTIDn(n=0 to 11) : Address Base addr + 1B
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
-
-
LID5
LID4
LID3
LID2
LID1
LID0
0
0
0
0
0
0
0
0
Initial value
R0,W0 R0,W0 RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
[bit7, bit6] Reserved bit
This is a reserved bit. The read value is "0". Be sure to write "0" to this bit.
[bit5 to bit0] LID5 to LID0: LIN ID setting bit
(when the LIN ID are written):
When the LIN assist mode is set as master mode and LIN ID register use enable bit (LIDEN) is enabled,
these bits set a value of the transmission LIN ID.
Note:
⋅
Function of this register is effective only in the LIN assist mode (LAMCR:LAMEN="1").
⋅
Be sure to set this setting (SCR:LBR="1") before LIN Break activates.
LIN Assist Mode Reception ID Register (LAMRID)
• LAMRIDn(n=0 to 11) : Address Base addr + 1B
H
(Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
P1
P0
LID5
LID4
LID3
LID2
LID1
LID0
0
0
0
0
0
0
0
0
Initial value
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
Attribute
[bit7, bit6] P1, P0: LIN ID parity indication bit
(when parity is read):
In assist mode, these bits indicate a parity value of the received LIN ID.
[bit5 to bit0] LID5 to LID0: LIN ID setting bit
(when ID is read):
In assist mode, these bits indicate a value of the received LIN ID.
Note:
Function of this register is effective only in the LIN assist mode (LAMCR:LAMEN="1").
MB91520 Series
MN705-00010-1v0-E
1421