Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
117
Bit name
Function
bit6 ACT/SCC:
Operation
flag/repeat
start
condition
generation bit
This bit differs in meanings between read and write.
Read: ACT bit
Write: SCC bit
The ACT bit indicates whether the operation is in master mode or slave mode.
ACT bit set conditions:
(1) When outputting a start condition to I
2
C bus (master mode)
(2) When the slave address matches the address sent from the master (slave mode)
(3) When the reserved address was detected and an acknowledge response was sent
toward it (slave mode with MSS="0")
ACT bit reset conditions:
<Master mode>
(1) A stop condition detected
(2) Arbitration lost detected
(3) A bus error detected
(4) I
2
C interface disable (ISMK:EN bit="0")
<Slave mode>
(1) (Repeat) start condition detected
(2) A stop condition detected
(3) Reserved address detected state (IBSR:RSA="1") and no acknowledge response sent
(4) I
2
C interface disable (ISMK:EN bit="0")
(5) A bus error occurs (BER bit="1")
When in master mode, writing "1" to this bit executes a repeat start. Writing "0" to this bit
is ignored.
Notes:
⋅
Write "1" to the SCC bit while master mode is interrupted (MSS="1", ACT="1",
INT="1"). If the ACT bit is "1", writing "1" to the SCC bit clears the INT bit to "0".
⋅
Writing "1" to this bit is disabled during slave mode (MSS="0", ACT="1").
⋅
When you write "1" to the SCC bit and "0" to the MSS bit, the MSS bit will take
precedence.
⋅
For read-modify-write instructions, SCC bit will be read.
⋅
When both of conditions below are met, "1" will be set to INT bit and I
2
C bus will be
waited (SCL="L"). It is necessary to write "1" in the SCC bit again to generate the
repetition start condition, and to clear the INT bit.
⋅
"1" is written to the SCC bit during master mode interrupt (MSS="1", ACT="1",
INT="1", WSEL="1") in the eighth bit
⋅
NACK is received in the ninth bit
⋅
When you generate the repetition start condition while DMA mode is enabled
(SSR:DMA="1"), SSR:TBI bit is "1" and IBCR:INT bit is "0", follow the steps below.
1. Write "1" to the IBCR:INT bit.
2. Make sure that "1" has been set to the IBCR:INT bit.
3. Write a slave address to the TDR.
4. Set "1" to this bit.
⋅
To issue the repetition start condition when the DMA mode is permitted (SSR:DMA=1),
the SSR:TBI bit is "1" and the INT bit is "0", confirm that the INT bit is set to "1" after
"1" is written to the INT bit, write the slave address to TDR, and set "1" to this bit.
MB91520 Series
MN705-00010-1v0-E
1430