Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
128
4.5.4.
Receive Data Register/Transmit Data Register:
RDR/TDR
RDR/TDR
Receive data register and transmit data register are located within the same addresses. When read, it
functions as the receive data register and when written, it functions as the transmit data register. When FIFO
is enabled, the address of RDR/TDR will be the address for reading/writing FIFO.
Read
RDR1n-0n(n=3 to 8, 10, 11) : Address Base addr + 06
H
(Access: Byte,
Half-word, Word)
15
14
13
12
11
10
9
8
bit
-
0
0
0
0
0
0
0
0
Initial value
RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Initial value
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
The receive data register (RDR) is the data buffer register for serial data reception.
⋅
Serial data signals sent to the serial data line (SDA pin) are converted in the shift register and stored in
the receive data register (RDR).
⋅
When you receive the first byte*1, the least significant bit (RDR:D0) is the data direction bit.
⋅
When the received data is stored in the receive data register (RDR), the reception data full flag bit
(SSR:RDRF) will be set to "1".
⋅
The reception data full flag bit (SSR:RDRF) will be automatically cleared to "0" when the receive data
register (RDR) has been read out.
*1: The first byte: indicates data after the (repeat) start condition
Notes:
⋅
When you use reception FIFO, if received data in the reception FIFO reaches specified number, "1" will
be set to SSR:RDRF.
⋅
When you are using reception FIFO, if the reception FIFO becomes empty, SSR:RDRF will be cleared to
"0".
MB91520 Series
MN705-00010-1v0-E
1441