Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4.7.
DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-halt by NMI Register) . 321
4.8.
DMA Transfer Suppression Level Register : DILVR (DMA-halt by Interrupt Level Register)
...................................................................................................................................... 322
5.
O
PERATION
................................................................................................................................. 324
5.1.
Configuration.................................................................................................................. 325
5.1.1.
Common Items for All Channels ............................................................................................................ 326
5.1.2.
Separate Items for Each Channel ......................................................................................................... 327
5.1.3.
Operations ................................................................................................................................................ 331
6.
DMA
U
SAGE
E
XAMPLES
.............................................................................................................. 344
CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS ......................... 347
1.
O
VERVIEW
.................................................................................................................................. 348
2.
F
EATURES
................................................................................................................................... 349
2.1.
Transfer Request Generation Setting ............................................................................ 350
2.2.
Interrupt Clearing Setting ............................................................................................... 351
3.
C
ONFIGURATION
.......................................................................................................................... 352
4.
R
EGISTERS
................................................................................................................................. 353
4.1.
DMA Request Clear Register 0 : ICSEL0 (Interrupt Clear SELect register 0) ............... 355
4.2.
DMA Request Clear Register 1 : ICSEL1 (Interrupt Clear SELect register 1) ............... 356
4.3.
DMA Request Clear Register 2 : ICSEL2 (Interrupt Clear SELect register 2) ............... 357
4.4.
DMA Request Clear Register 3 : ICSEL3 (Interrupt Clear SELect register 3) ............... 358
4.5.
DMA Request Clear Register 5 : ICSEL5 (Interrupt Clear SELect register 5) ............... 359
4.6.
DMA Request Clear Register 6 : ICSEL6 (Interrupt Clear SELect register 6) ............... 360
4.7.
DMA Request Clear Register 7 : ICSEL7 (Interrupt Clear SELect register 7) ............... 361
4.8.
DMA Request Clear Register 8 : ICSEL8 (Interrupt Clear SELect register 8) ............... 362
4.9.
DMA Request Clear Register 9 : ICSEL9 (Interrupt Clear SELect register 9) ............... 363
4.10.
DMA Request Clear Register 10 : ICSEL10 (Interrupt Clear SELect register 10) ......... 364
4.11.
DMA Request Clear Register 11 : ICSEL11 (Interrupt Clear SELect register 11) ......... 365
4.12.
DMA Request Clear Register 13 : ICSEL13 (Interrupt Clear SELect register 13) ......... 366
4.13.
DMA Request Clear Register 14 : ICSEL14 (Interrupt Clear SELect register 14) ......... 367
4.14.
DMA Request Clear Register 15 : ICSEL15 (Interrupt Clear SELect register 15) ......... 368
4.15.
DMA Request Clear Register 16 : ICSEL16 (Interrupt Clear SELect register 16) ......... 369
4.16.
DMA Request Clear Register 17 : ICSEL17 (Interrupt Clear SELect register 17) ......... 370
4.17.
DMA Request Clear Register 18 : ICSEL18 (Interrupt Clear SELect register 18) ......... 371
4.18.
DMA Request Clear Register 19 : ICSEL19 (Interrupt Clear SELect register 19) ......... 372
4.19.
DMA Request Clear Register 20 : ICSEL20 (Interrupt Clear SELect register 20) ......... 373
4.20.
DMA Request Clear Register 21 : ICSEL21 (Interrupt Clear SELect register 21) ......... 374
4.21.
DMA Request Clear Register 22 : ICSEL22 (Interrupt Clear SELect register 22) ......... 375
4.22.
DMA Request Clear Register 23 : ICSEL23 (Interrupt Clear SELect register 23) ......... 376
4.23.
DMA Request Clear Register 24 : ICSEL24 (Interrupt Clear SELect register 24) ......... 377
4.24.
DMA Request Clear Register 25 : ICSEL25 (Interrupt Clear SELect register 25) ......... 378
4.25.
DMA Request Clear Register 26 : ICSEL26 (Interrupt Clear SELect register 26) ......... 380
4.26.
DMA Request Clear Register 27 : ICSEL27 (Interrupt Clear SELect register 27) ......... 381
4.27.
IO Transfer Request Setting Register 0 to 15 : IORR0 to 15 (IO triggered DMA Request
Register for ch. 0 to 15) ................................................................................................ 382
5.
O
PERATION
................................................................................................................................. 384
5.1.
Configuration.................................................................................................................. 385
5.2.
Notes .............................................................................................................................. 386
CHAPTER 10: FIXEDVECTOR FUNCTION ....................................................................................... 387
1.
O
VERVIEW
.................................................................................................................................. 388
2.
F
EATURES
................................................................................................................................... 389
3.
C
ONFIGURATION
.......................................................................................................................... 390
4.
R
EGISTERS
................................................................................................................................. 391
5.
O
PERATION
................................................................................................................................. 392
5.1.
Operation After Reset Released .................................................................................... 393
5.2.
Usage ............................................................................................................................. 394
6.
N
OTES
........................................................................................................................................ 395
MB91520 Series
MN705-00010-1v0-E
(13)