Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
181
6.1.1.
List of Interrupts of CSIO
Table 6-1 Interrupt Control Bits and Interrupt Factors of CSIO
Inter-
rupt
Type
Interrupt
request
flag bit
Flag
register Interrupt factor
Interrupt
source
enable
bit
Clearing of interrupt request flag
Recep-
tion
RDRF
SSR
1-byte reception
SCR:
RIE
Reading of receive data (RDR)
Reception of as much
data as specified by
FBYTE
Reading of receive data (RDR) until the reception
FIFO is emptied
Detection of reception
idle for 8-bit time or
more while there is
valid data in the
reception FIFO with
the FRIIE bit set to
"1".
ORE
SSR
Overrun error
Writing of "1" to the reception error flag clear bit
(SSR:REC)
Trans-
mission
TDRE
SSR Transmission register
is empty
SCR:
TIE
Writing of transmit data (TDR) or writing of "1"
to the transmission FIFO operation enable bit
while the transmission FIFO operation enable bit
is "0" and there is valid data in the transmission
FIFO (retransmission)*
1
TBI
SSR
No transmission
operation
SCR:
TBIE
Writing of transmit data (TDR) or writing of "1"
to the transmission FIFO operation enable bit
while the transmission FIFO operation enable bit
is "0" and there is valid data in the transmission
FIFO (retransmission)*
1
FDRQ
FCR1
The storage data value
of the transmission
FIFO is FTICR
setting value or less,
or empty
FCR1:
FTIE
Writing of "0" to the FIFO transmission data
request bit (FCR1:FDRQ) or transmission FIFO is
full
CSE
SSR
Serial chip select pin
is inactive while
transmitting in slave
mode (SCR:MS="1")
SACSR:
SCEIE
Writing "0" to the serial chip select flag bit
(SACSR:CSE)
Status
TINT SACSR
Serial Timer Register
(STMR) matched
Serial Timer
Comparison Register
(STMCR)
SACSR:
TINTE
Writing "0" to the timer interrupt flag bit
(SACSR:TINT)
*1: Set the TIE bit to "1" after the TDRE bit is cleared to "0".
MB91520 Series
MN705-00010-1v0-E
1494