Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
197
(3) While operating transmission/reception, the reception data will be sampled at a rising edge of the serial
clock output (SCK). Receiving the last bit of receiving data sets SSR:RDRF=1 and when the reception
interrupt is enabled (SCR:RIE=1), a reception interrupt request will be generated. At this time, the receive
data (RDR) can be read. Reading the received data (RDR) clears SSR:RDRF to "0".
(4) After the number of data set in the TBYTE is completed for transmission/reception,
transmission/reception operation will be terminated.
(5) After hold time for the serial chip select pin is passed after the transmission/reception operation, the serial
chip select pin (SCS) will become inactive. However, if serial chip select active level
(SCSCR:SCAM="1") is held at this time, the serial chip select pin (SCS) will remain active.
Continuous Data Transmission or Reception Wait Operation
(1) When a setup other than (ESCR.WT1, ESCR.WT0)= (0, 0) is used for continuous transmission or
reception, a wait will be inserted between frames.
■ ESCR.WT1=0, ESCR.WT0=1(for master)
SCK
1Byte
2Byte
1bit
■ ESCR.WT1=1, ESCR.WT0=0(for master)
SCK
1Byte
2Byte
2bit
■ ESCR.WT1=1, ESCR.WT0=1(for master)
SCK
1Byte
2Byte
3bit
TDRE
TDRE
TDRE
MB91520 Series
MN705-00010-1v0-E
1510