Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
215
6.2.4. SPI Transfer (II)
Features
Item
Description
1 Mark level of serial clock (SCK)
"L"
2 Transmission data output timing
SCK falling edge
3 Reception data sampling
SCK rising edge
4 Data length
5 to 16, 20, 24, 32 bits
Register Settings
The following table lists the register settings required for SPI Transfer (II).
SCR:SPI*
1
=1, SMR:MD2=0, MD1=1, MD0=0, SCINV*
1
=1
Master operations: SCR:MS=0, SMR:SCKE=1
Slave operations: SCR:MS=1, SMR:SCKE=0
*1) Bit settings depend on the condition. See Table 6-5 for details.
(Note)
Use proper usage for setting the registers other than the above.
SPI Transfer (II) Timing Chart (Serial Chip Select Pin Unused)
Figure 6-14 SPI Transfer (II) Timing Chart (Serial Chip Select Pin Unused)
● Transmission
operation
operation
SCK
SOUT
TDR RW
TXE
D0
D7
D1 D2 D3 D4 D5 D6
● Reception
operation
operation
SIN
RXE
Sampling
1
st
byte
RDRF
TDRE
D0 D1 D2 D3 D4 D5 D6
2
nd
byte
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
RDR RD
*A
*A:More than 4 machine cycles are necessary after writing to TDR for slave
transmission (MS=1, SCKE=0, SOE=1)
*B:
”H” when SCR:MS=0
D0 of the third byte when it is SCR:MS=1 and TDRE is
”L”
”H” when it is SCR:MS=1 and TDRE is ”H”
*B
D7
MB91520 Series
MN705-00010-1v0-E
1528