Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

6. Operation of CSIO

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

221

(3) Reception data is sampled by the rising edge of the serial clock (SCK) output. When the last bit of

reception data is received, SSR:RDRF=1 is set, and when reception interrupt is enabled (SCR:RIE=1), a

reception interrupt request is output. At this time, the reception data (RDR) can be read. When the

reception data is read, SSR:RDRF is cleared to "0".

(4) The transmission/reception operation is terminated after the data transmission/reception is completed as

many as the number of times set with TBYTE.

(5) Then, after the hold time of serial chip select pin has passed, the serial chip select pin (SCS) become

inactive. However, if the serial chip select active level (SCSCR:SCAM=1) is maintained at this time, the

serial chip select pin (SCS) maintains its active state.



Successive data transmission or reception wait operation

(1) If setting other than (ESCR.WT1, ESCR.WT0)=(0, 0) is specified for successive data transmission or

reception, a wait is inserted between frames.

■ ESCR.WT1=0, ESCR.WT0=1(for master)

SCK

1Byte

2Byte

1bit

■ ESCR.WT1=1, ESCR.WT0=0(for master)

SCK

1Byte

2Byte

2bit

■ ESCR.WT1=1, ESCR.WT0=1(for master)

SCK

1Byte

2Byte

3bit

TDRE

MB91520 Series

MN705-00010-1v0-E

1534