Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

6. Operation of CSIO

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

231

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Timing Adjustment of Serial Chip Select

When the serial chip select operation is enabled (SCSCR:CSENn="1") in master mode (SCR:MS=0), the

setup delay time, hold delay time, and deselection time can be adjusted by adjusting the serial chip select

timing register (SCSTR3 to SCSTR0).

Setup delay time

Time from the instant when the serial chip select pin becomes active to the instant when the serial clock is

output. See Figure 6-24 and Figure 6-25 for the specification of the setup delay time.

It can be adjusted by the chip select setup delay bit (SCSTR0:CSSU7 to CSSU0).

Hold delay time

Time from the instant when the serial clock output is completed to the instant when the serial chip select pin

becomes inactive. See Figure 6-24 and Figure 6-25 for the specification of the hold delay time.

It can be adjusted by the chip select hold delay bit (SCSTR1:CSHD7 to CSHD0).

Deselection time

Minimum time from the instant when the serial chip select pin becomes inactive to the next instant when

the pin turns active. Even if transmission data is written to the transmission data register (TDR) during the

deselection time, the serial chip select pin does not become active until the deselection time end. See Figure

6-24 and Figure 6-25 for the specification of the deselection time.

Figure 6-24 Timing Adjustment (Normal Transfer (SPI="0"), SCINV="0")

SCK

Hold

delay

Setup

delay

SCS output

D３

Transmission data

TDR RW

TBI

・・・

Deselect

Figure 6-25 Operation of Serial Chip Select (Master Transmission (MS="0"),

Normal Transfer (SPI="1"), SCINV="0")

Hold

delay

Setup

delay

SCS output

D３

Transmission data

TDR RW

TBI

・・・

Deselect

SCK

Note:

With the normal transfer (SPI=0) and no hold delay time (SCSTR1:CSHD7 to CSHD0="00"h), the chip

select pin may become inactive before the sampling of the last bit. In such cases, adjust by increasing the

value of SCSTR1:CSHD7 to CSHD0.

MB91520 Series

MN705-00010-1v0-E

1544