Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

7. Operation of LIN Interface (v2.1)

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

246

7.1.2. Reception Interrupts and Flag Setting Timing

Reception interrupts occur when the reception is completed (SSR:RDRF), when a reception error occurs

(SSR:ORE, FRE), or when LIN break Field is detected.



Reception Interrupts and Flag Setting Timing

When the first stop bit is detected, reception data is stored in the Receive data register (RDR). When

reception is completed (SSR:RDRF=1) or a reception error occurs (SSR:ORE, FRE=1), a corresponding

flag is set. If reception interrupts are enabled (SCR:RIE=1) at this time, a reception interrupt will occur.

Note:

When a reception error occurs, the data in the receive data register (RDR) becomes invalid.

Figure 7-1 Timing of each Flag Bit Setting

Timing to set RDRF (reception data full) flag bit

Reception data

RDRF

Reception interrupt generate

Timing to set FRE (framing error) flag bit

Reception data

RDRF

(note)
・

A framing error occurs when the first stop bit is at the “L” level.

・

RDRF is set to “1” and data is received even when a framing error occurs, but the reception data is invalid.

Reception interrupt generate

FRE

Timing to set ORE (overrun error) flag bit

Reception data

RDRF

ORE

ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP

(note)
An overrun error occurs when the next data is transferred the reception data is read (RDRF=1).

Note:

If a falling edge of serial data is detected at the same time as the sampling point of the stop bit or before one

to two bus clocks during reception, the data may not be received with the edge disabled. It is recommended

to leave a space between frames if successive frames are to be output.

MB91520 Series

MN705-00010-1v0-E

1559