Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

7. Operation of LIN Interface (v2.1)

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

250

7.1.4. Transmission Interrupts and Flag Setting Timing

Transmission interrupts occur either when transmission is started after transfer of transmission data from the

transmit data register (TDR) to the transmit shift register (SSR:TDRE=1) or when the transmission

operation is idle (SSR:TBI=1).



Transmission Interrupts and Flag Setting Timing



Timing of transmission data empty flag (TDRE) setting

When data written to the transmit data register (TDR) is transferred to the transmit shift register, writing of

next data is enabled (SSR:TDRE=1). If the transmission interrupt is enabled (SCR:TIE=1) at this time, a

transmission interrupt occurs. The TDRE bit, being a read-only bit, is cleared to "0" by writing of data to

the transmit data register (TDR).



Timing of transmission bus idle flag (TBI) setting

When the transmit data register is empty (TDRE=1) and no transmission operation is in progress, the

SSR:TBI bit is set to "1". If transmission bus idle interrupt is enabled (SCR:TBIE=1) at this time, a

transmission interrupt occurs. When transmission data is written to the transmit data register (TDR), the

TBI bit and the transmission interrupt request will be cleared.

Figure 7-4 Timing of TDRE and TBI Setting

Timing to set transmission data empty flag (TDRE)

Transmission data

TDRE

Writing to TDR

ST D0 D1 D2 D3

Generation of transmission interrupt

D4 D5 D6 D7 SP ST

D0 D1 D2

ST：start bit D0～D7：data bit SP：stop bit

Timing to set transmission bus idle flag (TBI)

Transmission data

TBI

Write to TDR

ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7

ST：start bit D0～D7：data bit SP：stop bit

Generation of transmission
interrupt by TBI bit

TDRE

MB91520 Series

MN705-00010-1v0-E

1563