Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
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CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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7.2.2. Reception Interrupts and Flag Setting Timing in Assist
Mode
Reception interrupts occur when the reception is completed (SSR:RDRF) and when a reception error occurs
(SSR:ORE, FRE,LAMESR:LBSER,LSFER,LPTER,LCSER).
Reception Interrupts and Flag Setting Timing
In the LIN assist mode (LAMCR:LAMEN=1), received data is stored in the reception data register (RDR)
when the first stop bit of each of the following field is detected:
- ID Field which is under both the conditions that:
The multi-function serial interface is in slave mode (SCR:MS=1).
The data reception register (RDR) is set to be used in order to receive the ID Field
- Data Field for response.
When the reception of data is completed (SSR:RDRF=1), the data full flag bit is set. If the reception
interrupt is enabled (SSR:RIE=1), then the reception interrupt occurs.
As for the timing of setting the reception data full flag bit (SSR:RDRF), the timing is similar to those
described in "7.1.2 Reception Interrupts and Flag Setting Timing" in manual mode. See Figure-7.1.
Notes:
⋅
When the reception error occurs, the received data stored in the reception data register (RDR) becomes
invalid.
⋅
When the LIN assist mode reception ID register is used in order to receive the ID Field
(LAMCR:LIDEN=1), the received ID value is not stored in the reception data register (RDR) , and the
reception data full flag bit (SSR:RDRF) is not set.
⋅
Neither the Sync Field nor the checksum are stored in the reception data register (RDR), and the
reception data full flag bit (SSR:RDRF) is not set.
⋅
Those data transmitted from each field are not stored in the reception data register (RDR), and reception
data full flag bit (SSR:RDRF) is not set.
Framing Error Interrupt and Flag Setting Timing
In assist mode (LAMCR:LAMEN=1), the framing error is detected and a flag of the framing error is set
(SSR:FRE=1) when "L" level is detected in the stop bit of the Sync Field, the ID Field, the Data Field, and
the Check Sum Field, respectively. If the reception interrupt is enabled (SSR:RIE=1), the reception interrupt
will occur.
Moreover, when the framing error is detected, transmission/reception of both the header and the response is
stopped in the assist mode.
While the framing error flag is being set (SSR:FRE=1), the operation enable bit of the reception FIFO is
cleared (FCR0:FE1=0 or FCR0:FE2=0).
As for the timing of setting the framing error flag bit (SSR:FRE), the timing is similar to those described in
"7.1.2 Reception Interrupts and Flag Setting Timing" in manual mode. See Figure-7.1.
Overrun Error Interrupt and Flag Set Timing
When reception of data is detected before the previously received data is read (RDRF=1), the overrun error
is detected. After the reception of the next data is completed (SSR:RDRF=1), the overrun error flag is set
(SSR:ORE=1). If the reception interrupt is enabled (SSR:RIE=1), the reception interrupt occurs.
Moreover, when the overrun error is detected, transmission/reception of both the header and the response is
stopped in the assist mode.
MB91520 Series
MN705-00010-1v0-E
1570