Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
[bit12] UIE (User Mode Instruction Fetch Enable)
This bit is for permitting instruction fetch in user mode from the default areas (areas that have not been
specified as protection areas).
UIE
Access to default area
0
Instruction Fetch not enable at User Mode (Initial value)
1
Instruction Fetch enable at User Mode
[bit11] URE (User Mode Read Access Enable)
This bit is for permitting data read access in user mode from the default areas (areas that have not been
specified as protection areas).
URE
Access to default area
0
Read access not permitted in user mode (Initial value)
1
Read access permitted in user mode
[bit10] UWE (User Mode Write Access Enable)
This bit is for permitting data write access in user mode to the default areas (areas that have not been
specified as protection areas).
UWE
Access to default area
0
Write access not permitted in user mode (Initial value)
1
Write access permitted in user mode
[bit9] Reserved
Always write "0" when writing. This bit reads out "0".
[bit8] BE (Buffer Enable)
The bit permits buffering to be used when performing data access to default areas (areas that are not
specified as protection areas). When the use of buffering is forbidden, the CPU stops pipeline operation and
waits for the data access to finish before starting the next operation. As a result, although the data access
efficiency decreases, it is possible to perform data access synchronized to the instruction. Illegal instruction
exceptions occur when there is an error during data access only if buffering is forbidden. When buffering is
permitted, data access errors can be notified as interrupts.
BE
Buffer enable specification for the default area
0
Buffer disabled (Initial value)
1
Buffer enabled
[bit7 to bit4] Reserved
These bits are reserved. Always write "0" when writing.
MB91520 Series
MN705-00010-1v0-E
126