Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
297
Figure 7-45 From ID Field transmission to DATA Field reception (FIFO unused when ID
register is not used)
register is not used)
SSR : RDRF
Sync Field
DATA Field read
ID Field
data Field
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
L : TDR use
LAMTID : LID5-0
RDR
Data 1
Data (N-2)
checksum
Data 1
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
SSR : TDRE
Data (N-1)
Data N
ID Field value
：Don’t care
LAMSR : LCSC
LAMSR : LAHC
Notes:
The noise filter (The serial data input is sampled three times with the bus clock and decision by majority)
is built into. However, please design the board so that the noise should not pass this filter or
communicate by noise passing so as not to become a problem (For instance, when the noise error is
detected by adding checksum at the end of data, data is retransmitted.).
communicate by noise passing so as not to become a problem (For instance, when the noise error is
detected by adding checksum at the end of data, data is retransmitted.).
The falling edge becomes invalid and the next frame cannot be normally received when the falling edge
of the serial data is detected at the same time as the sampling point of the stop bit or before 1 to 2 bus
clocks when reception. When the frame is continuously output, the interval of the frame is recommended
to be opened.
clocks when reception. When the frame is continuously output, the interval of the frame is recommended
to be opened.
The checksum value of the response reception when the assist mode operates is not stored in the RDR
register.
The checksum value becomes the following when the LIN data length is set by 0 byte length
(LAMCR:LDL3-0="0000").
When the standard checksum is set (LAMCR:LCSTYP=0), the checksum value becomes 0xFF.
When the expanded checksum is set (LAMCR:LCSTYP=1), the checksum value becomes reversing
ID Field.
ID Field.
Master operation timing chart (When FIFO unused).
Figure 7-46 LIN bus timing (ID register use, DATA Field transmission, and FIFO unused)
LIN bus
LIN Break
LIN Break
delimiter
SCR : RXE
SSR : RDRF
Sync Field
SCR : LBR
SCR : TIE
SCR : RIE
SCR : TXE
ID Field value
LAMTID
SSR : TDRE
ID Field
Data 1
Data 2
Data 3
Data (N-2)
TDR
LAMCR : LIDEN
TDR write
ID Field value is
ID register use
ID register use
ID Field value is
Setting for ID register
Setting for ID register
Transmission interrupt generation：
DATA Field set
DATA Field set
Data 1
Data 2
Data 3
Data 4
Data (N-1)
LIN Break start
LAMCR : LAMEN
H : assist mode processing enable
LAMSR : LAHC
LIN auto header
Transmission complete flag
Transmission complete flag
H : ID register use
Response
space
checksum
Data N
Data (N-1)
Data N
checksum
H : transmission enable
：Don’t care
LAMSR : LCSC
H : transmission interrupt enable
SSR : TBI
L : transmission disable
L : reception interrupt disable
L : reception disable
MB91520 Series
MN705-00010-1v0-E
1610