Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
303
5. When the automatic header reception in the LIN assist mode is completed, the LAMSR:LAHC bit is
set to "1". Also when the LIN parity error is generated by ID Field, the LAMSR:LAHC bit becomes
"1". Therefore, when the LAMSR:LAHC bit is set to "1", it is necessary to confirm the error has not
been detected.
6. Please set LIN data length setting bit (LAMCR:LDL2 to LDL0) when ID Field is normally received.
Figure 7-56 From LIN Break Field reception to ID Field reception (parity error is generated).
LIN Break
LIN Break
delimiter
Sync Field
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP
ID Field
LIN bus
(1)
(2)
(5)
(3)(4)
SACSR : BST
BGR1, BGR0
LAMSR : LAHC
LAMESR : LPTER
ST 0 1 2 3 4 5 6 7 SP
data
Figure 7-57 From LIN Break Field reception to ID Field reception (set the LIN data length).
LIN Break
LIN Break
delimiter
Sync Field
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP
ID Field
LIN bus
(1)
(2)
(5)(6)
(3)(4)
SACSR : BST
BGR1, BGR0
LAMSR : LAHC
LAMCR : LDL3～LDL0
ST 0 1 2 3 4 5 6 7 SP
data
： Don’t care
LIN data length setting
Notes
⋅
The setting of reception enable bit (SCR:RXE) and transmission enable bit (SCR:TXE) is disregarded
during the header reception of the master in the assist mode.
⋅
However, when LIN Break Field is received, it is judged that the stop bit is "L" level before LIN Break is
detected and detects the framing error when the reception enable setting (SCR:RXE=1). Therefore,
please set to reception prohibition setting (SCR:RXE=0) when the header is transmitted.
⋅
The Sync Field value when the assist mode operates cannot be stored in the RDR register.
From ID Field reception to DATA Field transmission/reception
Whether DATA Field is transmitted or received to the master can be selected after ID Field reception.
(When DATA Field is transmitted)
⋅
Please write data in transmission data register (TDR) after reception ID Field. At this time, please make it
to transmission interrupt enable (SCR:TIE=1).
⋅
Please set LIN data length setting bit (LAMCR:LDL2 to LDL0) from the value of reception ID Field.
⋅
Checksum is operated based on LIN data length setting bit (LAMCR:LDL2 to LDL0), and after final
data is transmitted, checksum is transmitted automatically.
⋅
The arithmetic operations of checksum can select the arithmetic operations method by LIN checksum
type selection bit (LAMCR:LCSTYP).
⋅
When the arithmetic operations of checksum is completed, checksum arithmetic operations completion
flag (LAMCR:LCSC) is set. At this time, when the checksum arithmetic operations completion interrupt
enable bit is set (LAMIER:LCSCIE=1), the status interrupt is generated.
⋅
After the response transmission is completed (LAMSR:LCSC=1), transmission prohibition setting
(SCR:TXE=0) is done.
MB91520 Series
MN705-00010-1v0-E
1616