Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
304
Notes:
The response transmission data (Data Field and checksum) when the assist mode operates cannot be
stored in the RDR register.
When the response transmission, please write the dummy (the writing value is "don 't care") in the TDR
register to operate checksum automatically when the LIN data length is set to 0 byte length
(LAMCR:LDL3-0="0000") and to transmit. The TDR setting value at this time doesn't influence the
checksum arithmetic operations.
(LAMCR:LDL3-0="0000") and to transmit. The TDR setting value at this time doesn't influence the
checksum arithmetic operations.
The checksum value becomes the following when the LIN data length is set by 0 byte length
(LAMCR:LDL3-0="0000").
When the standard checksum is set (LAMCR:LCSTYP=0), the checksum value becomes 0xFF.
When the expanded checksum is set (LAMCR:LCSTYP=1), the checksum value becomes reversing
ID Field.
ID Field.
Figure 7-58 From ID Field reception to DATA Field transmission (ID register use).
SSR:TDRE
Sync Field
SCR : RIE
ID Field
data
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
H : LIN ID register use enable
TDR write
checksum
Data １
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LAHC
LAMRID : LID5-0
ID Field value
SCR : TXE
H : transmission enable
L : transmission disable
SCR : TIE
L : transmission interrupt disable
H : transmission interrupt enable
SCR : RXE
SSR : RDRF
L : reception disable
L : reception interrupt disable
： Don’t care
RDR
TDR
Data N
Data 2
LAMCR : LDL3-0
Data length setting
Data 1
Figure 7-59 From ID Field reception to DATA Field transmission (ID register unused).
SSR:TDRE
Sync Field
SCR : RIE
ID Field
data
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
L : LIN ID register use disable
TDR write
： Don’t care
checksum
Data １
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LAHC
LAMRID : LID5-0
SCR : TXE
H : transmission enable
L : transmission disable
SCR : TIE
L : transmission interrupt disable
H : transmission interrupt enable
SCR : RXE
SSR : RDRF
L : reception disable
L : reception interrupt disable
RDR
LAMCR : LDL3-0
Data length setting
TDR
Data １
Data N
Data 2
ID Field
(When receive DATA Field)
Please set LIN data length setting bit (LAMCR:LDL2 to LDL0) from the value of reception ID Field.
Please set the reception enable (SCR:RXE=1).
SSR:RDRF is set to "1" at each DATA Field reception. At this time, if reception interrupt enable
(SCR:RDIE=1) is done, the reception interrupt is generated.
Detection of the start bit is as follows; the falling edge is detected after passing through the noise filter
(which samples serial data input in 3 bus clock and decides the value by majority), and the data "L" is
detected after the noise filter at the sampling point.
detected after the noise filter at the sampling point.
MB91520 Series
MN705-00010-1v0-E
1617