Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

8. Operation of I2C

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

324

Interrupt

type

Interrupt

request

flag bit

Flag

Interrupt factor

Interrupt

factor

enable bit

Clearing of interrupt request

flag

Reception

RDRF

SSR

Reserved address

received

SMR:RIE

Reading of receive data (RDR)

After data reception

Reception of as much

data as specified by

FBYTE

Reading of receive data (RDR)

until the reception FIFO is emptied

Reception idle detected

by FBIIE="1"

ORE

SSR

Overrun error

Writing of "1" to the reception error

flag bit (SSR:REC)

Transmis-

sion

TDRE

SSR

Transmission register is

empty

SMR:TIE

Write to the transmit data (TDR),

or write "1" to the transmission

FIFO operation enable bit when it

is "0" and the transmission FIFO

has a valid data (retransmission)

Writing of "1" to the

transmission buffer

empty flag set bit

(SSR:TSET)

FDRQ

FCR1

The storage data value of

the transmission FIFO is

FTICR setting value or

less, or empty

FCR1:FTIE

Writing of "0" to the FIFO

transmission data request bit or the

transmission FIFO is full

TBI

(SSR:

DMA=1)

SSR

No transmission

operation

SCR:TBIE

Write to the transmit data (TDR),

or write "1" to the transmission

FIFO operation enable bit when it

is "0" and the transmission FIFO

has a valid data (retransmission)

Writing of "1" to the

transmission buffer

empty flag set bit

(SSR:TSET)

*1: No interrupt occurs if normal data can be transmitted/received and TDRE is "0". The purpose of this is to

support DMA transfer. If you want to generate the IBCR:INT flag when data is transmitted or received, the

SSR:TDRE bit must be "1" before the IBCR:INT flag is set.

*2: Set the SMR:TIE bit to "1" after the SSR:TDRE bit is cleared to "0".

*3: Set the SSR:TBIE bit to "1" after the SSR:TBI bit is cleared to "0".

MB91520 Series

MN705-00010-1v0-E

1637