Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
337
Table 8-4 Operation after Acknowledge Reception (when DMA mode is disabled)
(IBSR:RSA="0", SSR:DMA="1")
Trans-
missio
n FIFO
operati
on
Recep-
tion
FIFO
operati
on
Trans-
mission
FIFO
status
Recep-
tion
FIFO
status
Data
direction
bit (R/W)
Operation immediately after acknowledge
reception
Acknowledge is ACK
Acknowledge
is ACK
Disabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
The IBCR:INT bit
is set to "1" and
waited.
1
Disabled Enabled
-
Without
data
0
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
The IBCR:INT bit
is set to "1" and
waited.
With
data
The IBCR:INT bit is set to "1" and waited.
-
1
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
Enabled Disabled
-
-
0
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
The IBCR:INT bit
is set to "1" and
waited.
1
Enabled Enabled
-
Without
data
0
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
The IBCR:INT bit
is set to "1" and
waited.
With
data
The IBCR:INT bit is set to "1" and waited.
-
1
If the SSR:TDRE bit is "1", the SSR:TBI
bit is set to "1" and waited. If the
SSR:TDRE bit is "0", the SSR:TBI bit is
held to "0" and not waited.
MB91520 Series
MN705-00010-1v0-E
1650