Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
339
DMA Mode Enabled (SSR:DMA=1)
FIFO Disabled (Both Transmission and Reception FIFOs Disabled)
⋅
If the IBSR:RSA bit is "0", the transmission bus idle flag (SSR:TBI) is set to "1" and SCL is held to
"L" and waited if the SSR:TDRE bit is "1" after acknowledge reception. If the data transmitted to the
TDR register is written, the transmission bus idle flag becomes "0" and waiting is released. If the
SSR:TDRE bit is "0", the reception of ACK causes clock generation on SCL without setting the
transmission bus idle flag (SSR:TBI) to "1".
⋅
If the IBSR:RSA bit is "1", the interrupt flag (IBCR:INT) is set to "1" and SCL is held to "L" and
waited after reserved address reception (before acknowledge). After the RDR register is read, the
interrupt flag becomes "0" to release the wait when you set the IBCR:ACKE bit and the transmission
data, and write "0" to the interrupt flag.
⋅
The received acknowledge is set to the IBSR:RACK bit. The IBSR:RACK bit is checked during wait
state. If it is NACK, "0" will be written to the IBCR:MSS bit or "1" is written to the IBCR:SCC bit to
generate a stop condition or a repeated start condition. At this time, the IBCR:INT bit will be
automatically cleared to "0".
FIFO Enabling
⋅
Before setting the IBCR:MSS bit to "1", it is necessary to configure the following FIFO settings:
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For transmission to the slave (data direction bit ="0"), set data including the slave address, etc. in the
transmission FIFO.
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For data reception from the slave (data direction bit ="1"), configure the FIFO byte count register to
specify the number of bytes to be received, write to the transmit data register using the slave address,
data direction bit, and number of dummy data to be received.
⋅
If the IBCR:RSA bit is "0", after receiving ACK as an acknowledge, does not set the interrupt flag
(IBCR:INT) to "1", but transmits/receives data according to the data direction bit (not waited). If
NACK is received, the interrupt flag (IBCR:INT) is set to "1" and SCL is held to "L" and waited.
⋅
The received acknowledge is set to the IBSR:RACK bit. The IBSR:RACK bit is checked during wait
state. If it is NACK, "0" is written to the IBCR:MSS bit or "1" is written to the IBCR:SCC bit to
generate a stop condition or a repeated start condition. At this time, the IBCR:INT bit is automatically
cleared to "0".
MB91520 Series
MN705-00010-1v0-E
1652