Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

8. Operation of I2C

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

344

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Data transmission to slave when DMA mode is disabled (SSR:DMA=0)

[1] Transmission to a destination that is not at the reserved address

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If transmission FIFO is disabled

(1)  Set the slave address (including the data direction bit) in the TDR register, and set the IBCR: MSS bit to "1".
(2)  Transmit the slave address and receive ACK. The interrupt flag (IBCR:INT) becomes "1".
(3)  Write transmission data in the TDR register.
(4)  Update the IBCR:WSEL bit and set the interrupt flag (IBCR:INT) to "0" to release the I

C bus from waiting state.

(5) Put the I

C bus in a wait by setting the interrupt flag to "1", after receiving an acknowledge upon the transmission

of one byte when IBCR:WSEL is set to "0", or immediately after one byte has been transmitted when

IBCR:WSEL is set to "1". Repeat steps (3) to (5) until the specified number of data have been transmitted.

However, if NACK is received after the bus is released from waiting state when IBCR:WSEL=1, another

interrupt will occur after acknowledge reception to make the bus wait.

(6) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start

condition.

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If transmission FIFO is enabled

(1)  Write the slave address (including the data direction bit) and transmission data in the TDR register.
(2)  Set the IBCR:WSEL bit and write "1" to the IBCR:MSS bit.
(3)  If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I

bus wait. If all responses received are ACK, set the interrupt flag to"1" after transmitting the last byte, according

to the IBCR:WSEL setting to make the I

C bus wait.

(4) Write"0" to the IBCR:MSS bit or "1" to IBCR:SCC bit to generate a stop or repeat start conditions.

[2] Transmission to the reserved address

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If transmission FIFO is disabled

(1)  Set the reserved address as the slave address in the TDR register and set the IBCR:MSS bit to "1".
(2)  Transmit the slave address. The interrupt flag (IBCR:INT) becomes "1".
(3)  Read the RDR register and confirm the reserved address.(*1)
(4)  Write transmission data in the TDR register.
(5)  Update the IBCR:WSEL bit and set the interrupt flag (IBCR:INT) to "0" to release the I

C bus from waiting state.

(6) Put the I

C bus in a wait by setting the interrupt flag to "1", after receiving an acknowledge upon the transmission

of one byte when IBCR:WSEL is set to "0", or immediately after one byte has been transmitted when

IBCR:WSEL is set to "1". Repeat steps (4) to (6) until the specified number of data have been transmitted.

However, if NACK is received after the bus is released from waiting state when IBCR:WSEL=1, another

interrupt will occur after acknowledge reception to make the bus wait.

(7) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start

condition.

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If transmission FIFO is enabled

(4) Write all transmission data in the TDR register (until the transmission FIFO becomes full if it can).
(5) If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I

bus wait. If all responses received are ACK, set the interrupt flag to"1" after transmitting the last byte, according

to the IBCR:WSEL setting to make the I

C bus wait.

(6) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start

condition.

*1: If any of following conditions is met, it is necessary to set the IBCR:ACKE bit and IBCR:WSEL bit to "1" and

determine whether the device is to work as the master or slave for subsequent data.

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Reserved address is a general-call address in a multi-master configuration

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An arbitration lost is detected and the device may work as the slave

MB91520 Series

MN705-00010-1v0-E

1657