Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
345
Data transmission to slave when DMA mode is enabled (SSR:DMA=1)
[1] Transmission to a destination that is not at the reserved address
⋅
If transmission FIFO is disabled
(1) Slave Address (The data direction bit is included) is set in the TDR register and set the IBCR: MSS bit to "1".
(2) Transmit the slave address and receive ACK. The transmission bus idle flag (SSR:TBI) becomes "1".
(3) The data transmitted to the TDR register is written and release the I
(2) Transmit the slave address and receive ACK. The transmission bus idle flag (SSR:TBI) becomes "1".
(3) The data transmitted to the TDR register is written and release the I
2
C bus from waiting state.
(4) Put the I
2
C bus in a wait by setting the transmission bus idle flag (SSR:TBI) to "1", after receiving an
acknowledge upon the transmission of one byte when IBCR:WSEL is set to "0", or immediately after one byte
has been transmitted when IBCR:WSEL is set to "1".
(5) The data transmitted to the TDR register is written and release the I
2
C bus from waiting state.
(6) Put the I
2
C bus in a wait by setting the transmission bus idle flag to "1", after receiving an acknowledge upon the
transmission of one byte when IBCR:WSEL is set to "0", or immediately after one byte has been transmitted
when IBCR:WSEL is set to "1". Repeat steps (6) to (7) until the specified number of data have been transmitted.
However, if NACK is received after the bus is released from waiting state when IBCR:WSEL=1, interrupt flag
(IBCR:INT) is set to "1" after acknowledge reception to make the bus wait.
(7) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start
condition.*
2
⋅
If transmission FIFO is enabled
(1) Slave Address (The data direction bit is included) and the transmission data are set in the TDR register.
(2) Set the IBCR:WSEL bit and the IBCR:MSS bit to "1".
(3) If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I
(2) Set the IBCR:WSEL bit and the IBCR:MSS bit to "1".
(3) If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I
2
C
bus wait. If all ACK responses are received, set the transmission bus idle flag (SSR:TBI) to"1" after transmitting
the last byte, according to the IBCR:WSEL setting to make the I
2
C bus wait.
(4) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start
condition.*
2
[2] Transmission to the reserved address
⋅
If transmission FIFO is disabled
(1) Set the reserved address as the slave address in the TDR register and set the IBCR:MSS bit to "1".
(2) Transmit the slave address. The interrupt flag (IBCR:INT) becomes "1".
(3) Read the RDR register and confirm the reserved address.*
(2) Transmit the slave address. The interrupt flag (IBCR:INT) becomes "1".
(3) Read the RDR register and confirm the reserved address.*
1
(4) Write transmission data in the TDR register.
(5) Update the IBCR:WSEL bit and set the interrupt flag (IBCR:INT) to "0" to release the I
(5) Update the IBCR:WSEL bit and set the interrupt flag (IBCR:INT) to "0" to release the I
2
C bus from waiting state.
(6) Put the I
2
C bus in a wait by setting the interrupt flag to "1", after receiving an acknowledge upon the transmission
of one byte when IBCR:WSEL is set to "0", or immediately after one byte has been transmitted when
IBCR:WSEL is set to "1".
(7) The data transmitted to the TDR register is written and release the I
2
C bus from waiting state.
(8) Put the I
2
C bus in a wait by setting the transmission bus idle flag to "1", after transmitting an acknowledge upon
the reception of one byte when IBCR:WSEL is set to "0", or immediately after one byte has been received when
IBCR:WSEL is set to "1". Repeat steps (7) to (8) until the specified number of data have been transmitted.
However, if NACK is received after the bus is released from waiting state when IBCR:WSEL=1, the interrupt
flag (IBCR:INT) is set to "1" after acknowledge reception to make the bus wait.
(9) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start
condition.*
2
⋅
If transmission FIFO is enabled
(1) Set the reserved address as the slave address in the TDR register and set the IBCR:MSS bit to "1".
(2) Transmit the slave address. The interrupt flag (IBCR:INT) becomes "1".
(3) Read the RDR register and confirm the reserved address.*
(2) Transmit the slave address. The interrupt flag (IBCR:INT) becomes "1".
(3) Read the RDR register and confirm the reserved address.*
1
(4) Write all transmission data in the TDR register (until the transmission FIFO becomes full if it can).
(5) If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I
(5) If NACK is received during transmission, set the interrupt flag (IBCR:INT) to "1" immediately to make the I
2
C
bus wait. If all responses received are ACK, set the interrupt flag (IBCR:INT) to"1" after transmitting the last
byte, according to the IBCR:WSEL setting to make the I
2
C bus wait.
(6) Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" to generate a stop condition or a repeated start
condition.*
2
MB91520 Series
MN705-00010-1v0-E
1658