Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
10.3.5.
Data Access Protection Violation Status Register :
DPVSR
DPVSR
The bit configuration of the data access protection violation status register is shown.
This register indicates the status when a data access protection violation occurs.
The content of this register is updated by hardware only when DPV=0. Writing "0" to DPV only is valid.
Writes to any other bits and writing "1" to DPV are ignored.
DPVSR : Address 0326
H
(Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RW[1:0]
SZ[1:0]
MD
Reserved
DPV
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX R,WX R,WX R,WX
R,WX R0,W0 R0,W0
R,W
[bit15 to bit8, bit2, bit1] Reserved
These bits are reserved. Always write 0 to these bits.
[bit7, bit6] RW[1:0] (Read/Write)
The access type when the violation occurred. When a read-modify-write is executed, because both read and
write access rights are required and the determination is made in the initial read cycle, RW=01
B
read
(read-modify-write) even if the violation occurs in the write part of the read-modify-write.
RW[1:0]
Access type
00
Read
01
Read ( Read-modify-write )
10
Write
11
Reserved
MB91520 Series
MN705-00010-1v0-E
132