Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
353
Figure 8-27 Master Transmission Interrupt (13)-when FIFO is Disabled
(SSR:DMA="1", IBCR:WSEL="1", IBSR:RSA="0", Intermediate NACK Response)
Figure 8-28 Master Transmission Interrupt (14)-when FIFO is Disabled
(SSR:DMA="1", IBCR:WSEL="1" −> "0", IBSR:RSA="0", ACK Response)
S Slave Address W ACK Data ACK Data ACK Data ACK P or Sr
□ □ □ □▲
① ② ② ③
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of CNDE = "1"
: Interrupt by TBIE= "1"
(1) An interrupt generated by slave address transmission + direction bit transmission +
acknowledgment reception
- Write INT = "0" after the transmission data is written to the transmission buffer
(2) An interrupt generated by 1 byte transmission
- Write WSEL="0", INT = "0" after the transmission data is written to the transmission buffer
(3) An interrupt generated by 1 byte transmission
- Set MSS = "0" or MSS = "1" and SCC = "1"
*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)
S
Slave Address W
ACK
Data
ACK
Data
ACK Data
NACK P or Sr
□
□
□
□
▲
①
②
②
②
③
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of CNDE = "1"
: Interrupt by TBIE= "1"
(1) An interrupt generated by slave address transmission + direction bit transmission +
acknowledgment reception
- Write INT = "0" after the transmission data is written to the TDR register
(2) An interrupt generated by 1 byte transmission
- Write INT = "0" after the transmission data is written to the TDR register
(3) An interrupt generated by NACK response
- Set MSS = "0" or MSS = "1" and SCC = "1"
*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)
□
MB91520 Series
MN705-00010-1v0-E
1666