Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
355
Figure 8-31 Master Transmission Interrupt (17)-when FIFO is Enabled
(SSR:DMA="1", IBCR:WSEL="1", IBSR:RSA="0" )
S Slave Address W ACK Data ACK Data ACK Data ACK P or Sr
□ □ ▲
① ②
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of CNDE = "1"
: Interrupt by TBIE= "1"
(1) An interrupt generated because the transmission FIFO is empty
- Write INT = "0" after the transmission data is written to the transmission FIFO
(2) An interrupt generated by the last byte transmission (transmission FIFO is empty)
- Set MSS = "0" or MSS = "1" and SCC = "1"
Figure 8-32 Master Transmission Interrupt (18)-when FIFO is Enabled
(SSR:DMA="1", IBCR:WSEL="1", IBSR:RSA="0", NACK Response)
S Slave Address W ACK Data ACK Data ACK Data NACK P or Sr
□ △▲
① ②
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
: Interrupt by TBIE= "1"
(1) An interrupt generated because the transmission FIFO is empty
- Write INT = "0" after the transmission data is written to the transmission FIFO
(2) An interrupt generated by NACK response
- Set MSS = "0" or MSS = "1" and SCC = "1"
MB91520 Series
MN705-00010-1v0-E
1668