Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

8. Operation of I2C

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

357

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If the send/receive FIFO operation is enabled.

(1) Set the receive data count to the FBYTE register.
(2) Write the slave address (including the data direction bit) and the dummy data (for the receive data size) into the

TDR register.

(3) Set the IBCR:MSS bit to "1".
(4) Respond with an ACK and continue data reception when the SSR:TDRE bit is kept "0". After receiving the

specified bytes of data (set by FBYTE), set the SSR:RDRF bit to "1". When the SSR:RDRF bit is set to "1", read

the RDR register.

(5) If the SSR:TDRE bit is set to "1" and if IBCR:WSEL="0", send a NACK response. If IBCR: WSEL="1", set the

interrupt flag to "1" immediately after 1 byte of data reception in order to wait the I

C bus.

(6) If IBCR:WSEL="1", set the IBCR:ACKE bit to "0". If IBCR:WSEL="0", the IBCR:ACKE bit needs not be set.

Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" in order to generate a stop condition or a repeated start

condition.

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When DMA mode is enable (SSR:DMA=1)

If the data direction bit (R/W) is "1", data sent from the slave device will be received.

When FIFO operation is disabled, the master device operation is as follows:

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If the SSR:TDRE bit is "1", the master device will generate a wait (SSR:TBI="1", SSR:RDRF="1")

each time it receives 1 byte of data. At this time when IBCR:WSEL bit is "1" means before a wait and

when IBCR:WSEL bit is "0" means after a wait, the master device responds with ACK or NACK by

the ACKE bit setting of IBCR register.

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If the SSR:TDRE bit is "0", the master device will generate a wait (SSR:RDRF="1") each time it

receives 1 byte of data. At this time when IBCR:WSEL bit is "1" means before a wait and when

IBCR:WSEL bit is "0" means after a wait, the master device responds with ACK or NACK by the

ACKE bit setting of IBCR register.

If FIFO operation is enabled, the SSR:RDRF bit is set when the same number of bytes as the received data

bytes is received. Set the transmission bus idle flag (SSR:TBI) while the SSR:TDRE bit is "1", to wait the

I2C bus. At this time the ACK will operate as follows. The data will be stored in the reception FIFO as

received data even if NACK is output.

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When IBCR:WSEL="0" and the SSR:TDRE bit is set to "1", a NACK response will be made when

received a NACK even if the setting is for ACKE bit.

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When WSEL = "1", a wait (SSR: TBI="1") is generated after the last byte is received so that set the

IBCR:ACKE bit during the wait, and then the ACK or NACK response is performed according to the

setting for the IBCR:ACKE bit once the transmission bus idle flag (SSR:TBI) is cleared.

The following explains the waiting by interrupt.

Table 8-8 WSEL Bit during Master Data Reception

WSEL

Operation

In the 2nd or subsequent byte, the transmission bus idle flag (SSR:TBI) is set to "1" and SCL

is set to "L" to go into the wait state when the SSR:TDRE bit is "1" after the acknowledgment.

In the 2nd or subsequent byte, the reception data full flag (SSR:RDRF) is set to "1" and SCL is

set to "L" to go into the wait state when the reception FIFO not used after the

acknowledgment.

In the 2nd or subsequent byte, interrupt flag (SSR:TBI) will be set to "1" and SCL will be set

to "L" to go into the wait state when the SSR:TDRE bit is "1"after the master receives 1 byte

data.

In the 2nd or subsequent byte, the reception data full flag (SSR:RDRF) is set to "1" and SCL is

set to "L" to go into the wait state when the reception FIFO not used.

MB91520 Series

MN705-00010-1v0-E

1670