Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
358
The following gives an example of procedure to receive data from the slave device.
⋅
If the receive FIFO operation is disabled.
(1) Set the slave address (including the data direction bit) in the TDR register, and set the IBCR:MSS bit to "1".
(2) Transmit the slave address and receive ACK. The transmission bus idle flag (SSR:TBI) becomes "1".
(3) The data transmitted to the TDR register is written, and release the I
(2) Transmit the slave address and receive ACK. The transmission bus idle flag (SSR:TBI) becomes "1".
(3) The data transmitted to the TDR register is written, and release the I
2
C bus from waiting state.
(4) After the reception of one byte, put the I
2
C bus in a wait by setting the transmission bus idle flag (SSR:TBI) and
reception data full flag (SSR:RDRF) *
2
to "1" with following conditions.
•
After transmitting an acknowledge when IBCR:WSEL="0"
•
Immediately after one byte data is received when IBCR:WSEL=1
(5) Update the IBCR:WSEL bit and RDR register is read, and the data of the dummy is written in the TDR register.
(6) After the reception of one byte, put the I
(6) After the reception of one byte, put the I
2
C bus in a wait by setting the transmission bus idle flag (SSR:TBI) and
reception data full flag (SSR:RDRF)*
2
to "1" with following conditions.
•
After transmitting an acknowledge when IBCR:WSEL="0"
•
Immediately after one byte data is received when IBCR:WSEL=1
Repeat 5. to 6. until specified number of data is received.
(7) After reception of the last data, send a NACK response, set the IBCR:MSS bit to "0" or set the IBCR: SCC bit to
"1" in order to generate a stop condition or a repeated start condition.
⋅
If the transmission/receive FIFO operation is enabled.
(1) Set the receive data count to the FBYTE register.
(2) Write the slave address (including the data direction bit) and the dummy data (for the receive data size) into the
(2) Write the slave address (including the data direction bit) and the dummy data (for the receive data size) into the
TDR register.
(3) If IBCR:WSEL="0", respond with NACK by the setting of the ACKE bit, and write "1" to the IBCR:MSS bit.
(4) Respond with an ACK and continue data reception when the SSR:TDRE bit is kept "0". After receiving the
(4) Respond with an ACK and continue data reception when the SSR:TDRE bit is kept "0". After receiving the
specified bytes of data (set by FBYTE), set the SSR:RDRF bit to "1". When the SSR:RDRF bit is set to "1", read
the RDR register.
(5) If the SSR:TDRE bit is set to "1" and if IBCR:WSEL="0", set the interrupt flag to "1" after sending a NACK
response in order to wait the I
2
C bus. If IBCR:WSEL="1", set the transmission bus idle flag (SSR: TBI) to "1"
immediately after 1 byte of data reception in order to wait the I
2
C bus.
(6) If IBCR:WSEL="1", set the IBCR:ACKE bit to "0". If IBCR:WSEL="0", the IBCR:ACKE bit needs not be set.
Set the IBCR:MSS bit to "0" or set the IBCR:SCC bit to "1" in order to generate a stop condition or a repeated start
condition.
*1: When you issue the repeat start condition when the DMA mode is permitted (SSR:DMA=1), the
SSR:TBI bit is "1" and the IBCR:INT bit is "0", follow the steps below.
1. Write "1" to IBCR:INT bit.
2. Make sure that "1" has been set to the IBCR:INT bit.
3. Write a slave address to the TDR.
4. Set "1" to the IBCR:SCC bit.
*2: The reception data full flag (SSR:RDRF) is set to "1" after one byte data received independent of the
IBCR:WSEL setting. When the reception data full flag (SSR:RDRF) is set to "1" after the second byte,
IBCR:WSEL="0" and after an ACK is transmitted while IBCR:WSEL="0", I
2
C bus will be waited
immediately after one byte data is received when IBCR:WSEL=1.
Notes:
⋅
If the 7-bit slave address detection is enabled (ISBA:SAEN="1"), you cannot specify a
7-bit slave address in the master mode.
⋅
If SSR:TDRE is "0", an acknowledge signal will be sent based on the IBCR:ACKE bit setting and the
subsequent process will be executed even if an overrun error occurs.
⋅
If you need to change the IBCR register during data sending or receiving, change it only when the
interrupt flag (IBCR:INT) is "1" or when the transmission bus idle flag (SSR:TBI="1") is "1" during
the DMA mode is enabled (SSR:DMA=1).
⋅
When the master device is receiving data and the DMA mode is disabled (SSR:DMA=0) and when
dummy data is written in the TDR register, the next data will be received with the interrupt flag
(IBCR:INT) still "0" when SSR:TDRE bit is "0" at the timing when the interrupt flag (IBCR:INT)
becomes "1".
MB91520 Series
MN705-00010-1v0-E
1671