Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
363
8.3.8. Repetition Start Condition Issue when DMA Mode
Enabled (SSR:DMA=1)
When the transmission bus is idle and the interrupt flag (IBCR:INT) is "0", if the slave address is written
in the TDR register, the transmission operation begins and the repetition start condition cannot be issued.
Because of this reason, follow the steps blow when you issue the repetition start condition when the
transmission bus is idle (SSR:TBI="1") and the interrupt flag (IBCR: INT) is "0".
1. Set "1" to the IBCR:INT bit. At this time, the SIRQ interrupt is not generated.
2. Make sure that "1" has been set to the IBCR:INT bit.
3. Write a slave address to the TDR.
4. Issue a repeat start (IBCR:SCC="1").
2. Make sure that "1" has been set to the IBCR:INT bit.
3. Write a slave address to the TDR.
4. Issue a repeat start (IBCR:SCC="1").
Figure 8-41 Repetition Start Condition Issue when DMA Mode is Enabled
(SSR:DMA="1", IBCR:WSEL="0", IBSR:RSA="0", ACK Response)
ACK
D0
TBI bit
TDRE bit
INT bit
D7
Write “1” to
SCC bit
SCC bit
Write “1” to
INT bit
INT bit
Write data to
TDR
TDR
Repetition start
condition issue
SIRQ
Not generated
interrupt
ACK
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
INT bit
reading
reading
It is confirmed to
be set to one.
MB91520 Series
MN705-00010-1v0-E
1676