Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
366
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Reserved address detected
If the first byte already matches the reserved address ("0000xxxx" or "1111xxxx"), the IBCR:INT bit is set
to "1" and the I
2
C bus is waited after receiving the 8-th bit of data. These operations are not associated with
a permission of transmit or receive FIFO operation. During this time, make following settings after read the
received data.
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If you operate the device as a slave one, set the IBCR:ACKE bit to "1" and check the data direction bit
(IBSR:TRX). If it is the transmission direction, write the send data in the TDR register and clear the
IBCR:INT bit. Then, the device operates as a slave one.
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If you don’t want operate the device as a slave one, set the IBCR:ACKE bit to "0" and clear the
IBCR:INT bit. The device will not operate as a slave one after an ACK is output.
8.4.2. Data Direction Bit
After the address reception, a data direction bit that determines the data transmission or reception is
received. If this bit is "0", it shows that the master transmits data, while the slave receives data.
8.4.3. Slave Mode Reception
If the slave address matches and if the data direction bit is "0", it indicates the data reception in the slave
mode. The following gives an example of procedure of data reception in the slave mode.
When DMA mode is disable (SSR:DMA=0)
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If the receive FIFO operation is disabled
(1) After sending an ACK signal, set the interrupt flag (IBCR:INT) to "1" to wait the I
2
C bus. You can
determine the interrupt occurrence due to slave address matching shown by IBCR:MSS bit, IBCR:ACT
bit and IBSR:FBT bit. Set the IBCR:ACKE bit to "1" and set the interrupt flag (IBCR:INT) to "0" to
release the I
2
C bus from the waiting state. See Table 8-9.
(2) After receiving one byte of data, set the interrupt flag (IBCR:INT) to "1" based on the IBCR:WSEL
setting, and wait the I
2
C bus.
(3) Read the received data from the RDR register, set the IBCR:ACKE bit, and set the interrupt flag
(IBCR:INT) to "0" to release the I
2
C bus from the waiting state.
(4) Repeat Steps (2) and (3) until the stop condition or the repeated start condition is detected.
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If the receive FIFO operation is enabled
(1) When a NACK signal is detected or when the reception FIFO memory is full, the interrupt flag
(IBCR:INT) is set to "1" and the I
2
C bus is waited. When the stop condition or the repeated start
condition is detected, the IBSR:SPC bit and IBSR:RSC bit are set to "1" but the interrupt flag
(IBCR:INT) is not set to "1" (and the I
2
C bus is not waited). If the value set in the FBYTE register
matches the number of received data, the reception FIFO sets the SSR:RDRF bit to "1". During this
time, if the SMR:RIE bit is "1", a reception interrupt occurs.
(2) If the interrupt flag (IBCR:INT) is set to "1", the received data is read from the RDR register. After
reading all data sets, set the interrupt flag to "0" and release the I
2
C bus from the waiting state. When
the stop condition or the repeated start condition is detected, all of the received data sets are read from
the RDR register, and the IBSR:SPC bit or IBSR:RSC bit is cleared to "0".
MB91520 Series
MN705-00010-1v0-E
1679