Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
10.3.7.
Data Access Error Status Register : DESR
The bit configuration of the data access error status register is shown.
This register indicates the status when a data access error occurs. The content of this register is updated by
hardware only when DAE=0. Writing 0 to DAE only is valid. Writes to any other bits and writing 1 to DAE
are ignored.
DESR : Address 032E
H
( Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RW[1:0]
SZ[1:0]
MD
Reserved
DAE
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX R,WX R,WX R,WX
R,WX R0,W0 R0,W0
R,W
[bit15 to bit8, bit2, bit1] Reserved
These bits are reserved. Always write 0 to these bits. These bits read out "0".
[bit7, bit6] RW[1:0] (Read/Write)
The access type when the error occurred.
RW[1:0]
Access type
00
Read
01
Read ( Read-modify-write )
10
Write
11
Reserved
[bit5, bit4] SZ[1:0]
The access size when the error occurred.
SZ[1:0]
Access size
00
Byte
01
Half-word
10
Word
11
Reserved
MB91520 Series
MN705-00010-1v0-E
135