Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.2.2. CAN Status Register : STATR
The bit configuration of the CAN status register is shown.
Displays the CAN and CAN bus statuses.
CAN Status Register (upper byte): Address Base + 02
H
(Access: Byte,
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
CAN Status Register (lower byte): Address Base + 03
H
(Access: Byte,
Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BOff
EWarn
EPass
RxOk
TxOk
LEC[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R,WX
R,WX
R,W
R,W
R,WX
R,WX
R,WX
[bit15 to bit8]: Reserved bit
The read value is always "0". When writing to these bits, set "0".
[bit7]: Bus-off bit
BOff
Function
0
Indicates the CAN controller is not in the bus-off state.
[Initial value]
1
Indicates the CAN controller is in the bus-off state.
[bit6]: Warning bit
EWarn
Function
0
Indicates both the transmission and reception counters are below 96.
[Initial value]
1
Indicates the transmission or reception counter is 96 or more.
[bit5]: Error passive bit
EPass
Function
0
Indicates both the transmission and reception counters are below 128 (error active state).
[Initial value]
1
Indicates the reception counter is the RP bit = "1" and the transmission counter is 128 or
more (error passive state).
MB91520 Series
MN705-00010-1v0-E
1712