Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
4.2.6. CAN Test Register : TESTR
The bit configuration of the CAN test register is shown.
Monitors the test mode setting and RX pins. For operation, see "5.7 Test Mode".
CAN Test Register (upper byte): Address Base + 0A
H
(Access: Byte, Half-word,
Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
CAN Test Register (lower byte): Address Base + 0B
H
(Access: Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Rx
Tx1
Tx0
LBack
Silent
Basic
Reserved Reserved
Initial value
r
0
0
0
0
0
0
0
Attribute R,WX
R/W
R/W
R/W
R/W
R/W
R0,W0
R0,W0
* The level on the CAN bus is displayed as the initial value (r) of Rx.
[bit15 to bit8] : Reserved bit
The read value is always "0". When writing to these bits, set "0".
[bit7] Rx : Rx pin monitor bit
Rx
Function
0
Indicates the CAN bus is dominant.
1
Indicates the CAN bus is recessive.
[bit6, bit5] Tx1, Tx0 : TX pin control bits
Tx1, Tx0
Function
00
Normal operation [Initial value]
01
Sampling points will be output to the TX pin.
10
Dominant will be output to the TX pin.
11
Recessive will be output to the TX pin.
MB91520 Series
MN705-00010-1v0-E
1718