Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
41
10.3.9.
Protection Area Control Register 0 to 7 : PACR0 to
PACR7
PACR7
The bit configuration of protection area control register 0 to 7 is shown.
These registers set access permissions and restrictions for each MPU channel.
PACR0 to PACR7 : Address 0336
H ,
033E
H ,
0346
H
• • • (Access : Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PIE
PRE
PWE
UIE
URE
UWE Reserv
ed
BE
Initial value
0
0
0
0
0
0
-
0
Attribute R/W
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ASZ[4:0]
Reserved
PAE
Initial value
0
0
0
0
0
-
-
0
Attribute R/W
R/W
R/W
R/W
R/W
R0,W0 R0,W0
R/W
[bit15] PIE (Privilege Mode Instruction Fetch Enable)
This bit is for enabling instruction fetch in privilege mode for the specified protection area.
PIE
Access to the specified protection area
0
Instruction fetch not permitted in privilege mode (Initial value)
1
Instruction fetch permitted in privilege mode
[bit14] PRE (Privilege Mode Read Access Enable)
This bit is for enabling data read access in privilege mode for the specified protection area.
PRE
Access to the specified protection area
0
Read access not permitted in privilege mode (Initial value)
1
Read access permitted in privilege mode
[bit13] PWE (Privilege Mode Write Access Enable)
This bit is for enabling data write access in privilege mode for the specified protection area.
PWE
Access to the specified protection area
0
Write access not permitted in privilege mode (initial value)
1
Write access permitted in privilege mode
MB91520 Series
MN705-00010-1v0-E
138