Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.3.1. IFx Command Request Register : IFxCREQ
The bit configuration of the IFx command request register is shown.
Selects the message number of the message RAM and transfers the message between the message RAM
and the message buffer register. In addition, IF1 is used for transmission control and IF2 is used for
reception control in the basic mode for tests.
IFx Command Request Register (upper byte): Address Base + 10
H
& Base +
40
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BUSY Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
IFx Command Request Register (lower byte): Address Base + 11
H
& Base +
41
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Message Number
Initial value
0
0
0
0
0
0
0
1
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Immediately after the message number is written into the IFx command request register (IFxCREQ), the
message transfer between the message RAM and the message buffer register (mask, arbitration, message
control and data register) is started. This writing operation indicates that "1" is set to the BUSY bit and a
message is being transferred. When the transfer is completed, the BUSY bit is reset to "0".
When "1" is set to the BUSY bit, the CPU will be kept waiting until the BUSY bit becomes "0" if the CPU
accesses to the message interface register (3 to 6 clock cycles after writing into the command request
register).
The BUSY bit is used differently in the basic mode for tests. The IF1 command request register is used as a
transmission message, and setting "1" to the BUSY bit directs message transmission start. When the
message transfer is completed successfully, the BUSY bit is reset to "0". In addition, resetting the BUSY bit
to "0" aborts message transfer at any time.
The IF2 command request register is used as a reception message, and setting "1" to the BUSY bit stores the
received message in the IF2 message interface register.
[bit15] BUSY : Busy flag bit
(1) Other than test basic mode
BUSY
Function
0
Indicates that data is not being transferred between the message interface register and
the message RAM. [Initial value]
1
Indicates that data is being transferred between the message interface register and the
message RAM.
MB91520 Series
MN705-00010-1v0-E
1722