Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
52
Set/reset conditions of the NewDat bits are shown below.
Set condition
When the WR/RD of the IFx command mask register (IFxCMSK) is set to "1", the Control is set to
"1", and the NewDat of the IFx message control register (IFxMCTR) is set to "1", it is possible to set
a specific object by writing data to the IFx command request register (IFxCREQ).
The bit will be set by a reception of data frame that has passed the acceptance filter.
When the Dir is set to "1", the RmtEN is set to "0", and the UMask is set to "1", the bit will be set by
a reception of remote frame that has passed the acceptance filter.
Reset condition
When the WR/RD of the IFx command mask register (IFxCMSK) is set to "0" and the NewDat is set
to "1", it is possible to reset the NewDat of a specific object by writing data to the IFx command
request register (IFxCREQ).
When the WR/RD of the IFx command mask register (IFxCMSK) is set to "1", the Control is set to
"1", and the NewDat of the IFx message control register (IFxMCTR) is set to "0", it is possible to
reset the NewDat of a specific object by writing data to the IFx command request register
(IFxCREQ).
It will be reset after data has been transferred to the transmission shift register (internal register).
See the following table to confirm the data update bit for CAN macro equipped with 128 message buffers.
Table 4-7 Data Update Bit for CAN Macro Equipped with 128 Message Buffers
addr + 0
addr + 1
addr + 2
addr + 3
NEWDT 6 & 5 NewDat 96 to 65
(address 98
H
)
NewDat96 to 89 NewDat88 to 81 NewDat80 to 73 NewDat72 to 65
NEWDT 8 & 7 NewDat 128 to 97
(address 9C
H
)
NewDat128 to
121
NewDat120 to
113
NewDat112 to
105
NewDat104 to
97
MB91520 Series
MN705-00010-1v0-E
1745