Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
55
Set/reset conditions of the IntPnd bits are shown below.
Set condition
If the TxIE is set to "1", the IntPnd bit will be set after the frame transmission has ended
successfully.
If the RxIE is set to "1", the bit will be set after the frame reception that has passed the acceptance
filter completed successfully.
When the WR/RD of the IFx command mask register (IFxCMSK) is set to "1", the Control is set to
"1", and the IntPnd of the IFx message control register is set to "1", it is possible to set the IntPnd of
a specific object by writing data to the IFx command request register (IFxCREQ).
Reset condition
When the WR/RD of the IFx command mask register (IFxCMSK) is set to "0" and the CIP is set to
"1", it is possible to reset the IntPnd of a specific object by writing data to the IFx command request
register (IFxCREQ). When the WR/RD of the IFx command mask register is set to "1", the Control
is set to "1", and the IntPnd of the IFx message control register (IFxMCTR) is set to "0", it is
possible to reset the IntPnd of a specific object by writing data to the IFx command request register.
See the following table to confirm the interrupt pending bit for CAN macro equipped with 128 message
buffers.
Table 4-8 Interrupt Pending Bit for CAN Macro Equipped with 128 Message Buffers
addr + 0
addr + 1
addr + 2
addr + 3
INTPND 6 & 5
IntPnd 96 to 65
(address A8
H
)
IntPnd96 to 89 IntPnd88 to 81 IntPnd80 to 73 IntPnd72 to 65
INTPND 8 & 7
IntPnd 128 to 97
(address AC
H
)
IntPnd128 to
121
IntPnd120 to
113
IntPnd112 to
105
IntPnd104 to 97
MB91520 Series
MN705-00010-1v0-E
1748