Fujitsu FR81S User Manual
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
58
Set/reset conditions of the MsgVal bits are shown below.
Set condition
When the WR/RD of the IFx command mask register is set to "1", the Arb is set to "1", and the
MsgVal bit of the IFx arbitration register 2 is set to "1", it is possible to set the MsgVal bit of a
specific object by writing data to the IFx command request register (IFxCREQ).
Reset condition
When the WR/RD of the IFx command mask register is set to "1", the Arb is set to "1", and the
MsgVal bit of the IFx arbitration register 2 is set to "0", it is possible to clear the MsgVal bit of a
specific object by writing data to the IFx command request register (IFxCREQ).
See the following table to confirm the message valid bit for CAN macro equipped with 128 message
buffers.
Table 4-9 Message Valid Bit for CAN Macro Equipped with 128 Message Buffers
addr + 0
addr + 1
addr + 2
addr + 3
MSGVAL 6 & 5
MsgVal 96 to 65
(address B8
H
)
MsgVal96 to 89 MsgVal88 to 81 MsgVal80 to 73 MsgVal72 to 65
MSGVAL 8 & 7 MsgVal 128 to 97
(address BC
H
)
MsgVal128 to
121
MsgVal120 to
113
MsgVal112 to
105
MsgVal104 to
97
MB91520 Series
MN705-00010-1v0-E
1751