Fujitsu FR81S User Manual
CHAPTER 41: CAN
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
76
5.4.1. Configuration of FIFO Buffer
The configuration of FIFO buffer is shown.
The configuration of the reception message objects in the FIFO buffer is the same as that of other reception
message objects, except for the EoB bit (see "5.3 Message Reception Operation" for the reception message
object setting).
FIFO buffer is used by linking 2 or more reception message objects. When using the ID and mask of the
reception message object, it is necessary to match those settings in order to store the reception message to
this FIFO buffer.
The first reception message object of the FIFO buffer will be the message object having the highest priority
(smallest message number). The EoB bit of the final reception message object of the FIFO buffer must be
set to "1" to indicate the end of the FIFO buffer block (Set The EoB bit to "0" for message objects other
than the final message object that uses the configuration of the FIFO buffer).
Notes:
⋅
Always make the same settings for ID and mask setting of the message object to be used in the FIFO
buffer.
⋅
Always set The EoB bit to "1" when FIFO buffer is not used.
MB91520 Series
MN705-00010-1v0-E
1769