Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
[bit14] INT : Interrupt request flag bit
INT
Function
Read
Write
0
A/D conversion is not completed.
Clear of bit
1
A/D conversion was completed.
This bit value does not change and there
is no influence on an operation by
writing.
When data is set in A/D data register (ADTCD) by the A/D conversion, this bit is set in "1".
When this bit and interrupt request enable bit (ADTCS:INTE) are "1", the request enable is generated.
This bit is cleared by writing "0". This bit value does not change and there is no influence on an
operation by writing "1".
When the A/D conversion completion interrupt clear signal is "H", this bit is cleared.
Note:
If the read-modify-write (RMW) instruction is executed, "1" will be read out.
If a software clear (write of “0”) or a clear due to an interrupt clear signal (“H”), and a hardware set occur at
the same time, the software clear (write of “0”) or the clear due to an interrupt clear signal (“H”) takes
precedence.
[bit13] INTE : Interrupt request enable bit
INTE
Function
0
Interrupt request output disable
1
Interrupt request output enable
This bit is the interrupt output enable/disable to CPU.
When this bit and interrupt request flag bit (ADTCS:INT) are "1", the interrupt request is generated.
[bit12, bit11] STS1, STS0 : A/D activation factor select bit
ADTECSn:
STS2
STS1
STS0
Function
0
0
0
Software trigger
0
0
1
External trigger activation (falling edge)
0
1
0
Reload timer activation (rising edge)
0
1
1
Compare match activation
1
0
0
PPG activation (rising edge)
1
0
1
Setting disable
1
1
0
1
1
1
The activation factor of A/D conversion is selected by the STS1, STS0 bit and bit8 (STS2) of A/D the
activation trigger extend control register (ADTECS).
MB91520 Series
MN705-00010-1v0-E
1834