Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
52
4.2.13.
Activation Channel Conversion Count Setting
Register : ADNCS0 to ADNCS23
The bit configuration of the activation channel conversion count setting register is shown.
The activation channel conversion count setting register (ADNCS) sets conversion count specification scan
conversion execution enable/disable select and the conversion count specification of each activation
channel.
ADNCSm(m = 0 to 15): Address 1448
H
to 1457
H
(Access: Byte, Half-word,
Word)
ADNCSn(n = 16 to 23): Address 15B4
H
to 15BB
H
(Access: Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CNTEN
(m*2+1)
Reserved
CCNT
(m*2+1)1
CCNT
(m*2+1)0
CNTEN
(m*2)
Reserved
CCNT
(m*2)1
CCNT
(m*2)0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,W0
R/W
R/W
R/W
R0,W0
R/W
R/W
[bit7, bit3] CNTEN : Conversion count specification scan conversion execution enable bit
CNTEN[n]
Explanation
0
Conversion count specification scan conversion execution disable
1
Conversion count specification scan conversion execution enable
(N= 0 to 47)
These bits can set conversion count specification scan conversion execution enable/disable of each
activation channel.
Only one scan conversion group can control the scan conversion of each channel by the conversion
count specification with each 12-bit A/D converter unit.
[bit6, bit2] Reserved
These bits must always be written to "0".
[bit5, bit4, bit1, bit0] CCNT : Conversion count specification bit
CCNT[n1]
CCNT[n]0
Explanation
0
0
1 time of conversion count instruction
0
1
2 times of conversion count instruction
1
0
3 times of conversion count instruction
1
1
4 times of conversion count instruction
(n= 0 to 47)
When the conversion count specification scan conversion execution of the activation channel is enabled,
the scan conversion count is controlled.
MB91520 Series
MN705-00010-1v0-E
1855