Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
61
4.3.3. A/D Mode Setting Register : ADMD
The bit configuration of the A/D mode setting register is shown.
The A/D mode setting register (ADMD) sets the compare time and the sampling time of the A/D
conversion.
ADMD0: Address 1463
H
(Access: Byte, Half-word, Word)
ADMD1: Address 15CE
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
STPCEN
Reserved
CT1
CT0
ST1
ST0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
[bit7] STPCEN : Sampling time setting per channel enable bit
STPCEN
Explanation
0
Sampling time setting of all channel commonness
1
Sampling time setting of each channel
This bit selects setting of each channel or setting of all channel commonness as the sampling time
setting in the A/D conversion.
When STPCEN="0", all channels are common the sampling time. The sampling time is set by the
sampling time set bit.
When STPCEN="1", the sampling time of each channel can be set. The sampling time of each channel is
set by the sampling time setting per channel enable bit.
[bit6 to bit4] Reserved
These bits must always be written to "0".
[bit3, bit2] CT1 , CT0 : Compare time setting bits
CT1
CT0
Function
0
0
28 Peripheral clock
(A/D clock output : Peripheral clock /2)
0
1
42 Peripheral clock
(A/D clock output : Peripheral clock /3)
1
0
56 Peripheral clock
(A/D clock output : Peripheral clock /4)
1
1
112 Peripheral clock
(A/D clock output : Peripheral clock /8)
These bits select the compare time in the A/D conversion.
After the analog input is taken (sampling time passage), the data of the conversion result is fixed After
the time set to these bits.
MB91520 Series
MN705-00010-1v0-E
1864