Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
64
4.3.4. A/D Sampling Time Setting Per Channel Register :
ADSTPCS
The bit configuration of the A/D sampling time setting per channel register is shown.
The A/D sampling time setting per channel register (ADSTPCS) sets the sampling time of the A/D
conversion of each channel.
ADSTPCSm (m=0 to 7): Address 1464
H
to 146B
H
(Access: Byte, Half-word,
Word)
ADSTPCSm (m=8 to 11): Address 15D0
H
to 15D3
H
(Access: Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
STCH
(m*4+3)1
STCH
(m*4+3)0
STCH
(m*4+2)1
STCH
(m*4+2)0
STCH
(m*4+1)1
STCH
(m*4+1)0
STCH
(m*4)1
STCH
(m*4)0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit0] STCHn1, STCHn0 (n=0 to 47) : Sampling time setting bits
STCHn1 STCHn0
Explanation
0
0
12 Peripheral clock
(A/D clock output : Peripheral clock /2)
0
1
18 Peripheral clock
(A/D clock output : Peripheral clock /3)
1
0
24 Peripheral clock
(A/D clock output : Peripheral clock /4)
1
1
48 Peripheral clock
(A/D clock output : Peripheral clock /8)
These bits select the sampling time in the A/D conversion.
The correspondence of a set channel and an analog channel is shown below.
MB91520 Series
MN705-00010-1v0-E
1867