Fujitsu FR81S User Manual
CHAPTER 44: 12-BIT A/D CONVERTER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 12-BIT A/D CONVERTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
79
5.2.8. Compare match activation
The compare match activation is explained.
The A/D activation trigger control factor select bit is set to compare match activation (ADTECS.STS2="0",
ADTCS.STS1, STS0="11
ADTCS.STS1, STS0="11
B
").
The compare register is in each activation channel. When 16-bit free-run timer matches to the compare
register value, the compare match activation request is set.
The timer value that activates is set to compare register. Please set "0000
register value, the compare match activation request is set.
The timer value that activates is set to compare register. Please set "0000
H
" when you want to do the A/D
activation request according to same timing of free-run timer as 0 detection. Moreover, please set the same
value as the compare clear value of free-run timer when you want to activate A/D according to same timing
of free-run timer as the compare clear.
value as the compare clear value of free-run timer when you want to activate A/D according to same timing
of free-run timer as the compare clear.
Operation mode of compare match activation
The operation mode of the A/D compare activation mode can be set by the SEL1,SEL0 bits of A/D
activation trigger control status register (ADTCS).
The comparison between the compare register value and the 16-bit free-run timer can set any of both
counting up and down, only counting up, or only counting down by the SEL1,SEL0 bits.
Moreover, even if the free-run timer is corresponding to compare register value, the activation request
signal is not generated for the A/D activation arbitration if the SEL1,SEL0 bits is set in "11
activation trigger control status register (ADTCS).
The comparison between the compare register value and the 16-bit free-run timer can set any of both
counting up and down, only counting up, or only counting down by the SEL1,SEL0 bits.
Moreover, even if the free-run timer is corresponding to compare register value, the activation request
signal is not generated for the A/D activation arbitration if the SEL1,SEL0 bits is set in "11
B
".
SEL1, SEL0=00
B
: Compare match activation
Figure 5-1 SEL1, SEL0="00
B
": Compare match activation when both counting up and down
Compare value
Count value
time
A/D activation request
A/D activation request
A/D activation request
A/Dactivation request
SEL1, SEL0=01
B
: Compare match activation when only counting up
Figure 5-2 SEL1, SEL0=01
B
: Compare match activation when only counting up
Compare value
Count value
time
A/D activation request
A/D activation request
MB91520 Series
MN705-00010-1v0-E
1882