Fujitsu FR81S User Manual
CHAPTER 45: FLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
5.2. Programming Flash Memory by CPU
This section explains programming flash memory by CPU.
After configuring CPU programming mode, perform erasing and programming using the automatic
algorithm. In this model, because error correction codes (ECC) are added to each single word, programming
needs to be performed for each single word. In the following procedure, each word is programmed by two
operations to write one half-word. If this procedure is not followed, the written values will not be read
correctly because the values will be written to flash memory without calculating the ECC.
1. Set the flash access size to 16 bits. (FCTLR:FSZ[1:0]=01)
2.
Issue the write command. Write address = PA, write data = PD[31:16]
See "5.5.
Write Command
" for
details on the write command.
3.
Read the hardware sequence flag until the write has finished. See "5.3.2. Automatic Algorithm
Execution State" for details on reading the hardware sequence
flag.
4. Issue the write command. Write address = PA+2, write data = PD[15:0] At this time, the hardware
automatically calculates the ECC codes by combining with PD[31:16] from (2), and writing of ECC
codes is also performed automatically at the same time.
5. Read the hardware sequence flag until the write has finished.
6. If there is more data to write, return to (2). Continue to (7) when all writes have finished.
7. Set CPU-ROM mode
8. Read the value which has already been written, and check that the correct value can be read. Even if
the correct value can be read, check the FSTR:FECCERR bit to make sure that there was no ECC
correction. If ECC correction occurs, follow the same procedure again starting from erasing the flash
memory.
PA: Write target address (word aligned)
PD[31:0]: Write data
PD[31:16]: Write data upper 16 bits
PD[15:0]: Write data lower 16 bits
MB91520 Series
MN705-00010-1v0-E
1949