Fujitsu FR81S User Manual
CHAPTER 45: FLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
Notes:
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Once the write has finished, because the flash memory returns to read mode, write addresses are no
longer accepted.
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See "5.3 Automatic Algorithm" for details on write commands.
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Because the DPOLL bit and the TLOV bit of the hardware sequence flag change at the same time, even
when the TLOV bit is "1", it is necessary to confirm again.
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When the TOGG1 bit and the TLOV bit of the hardware sequence flag change to "1", the toggle
operation stops at the same time. Therefore, it is necessary to confirm the TOGG1 bit again even the
TLOV bit is "1".
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Although flash memory can be written to in any order of addresses, even if it crosses a sector boundary,
only a single half-word data can be written in each write command sequence. If you want to write
multiple data, issue one write command sequence for each data.
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Data that has been written to "0" once cannot be returned to "1". If "0" is rewritten with "1", one of the
following occurs.
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The element is judged as faulty by the data polling algorithm.
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The write rated time is exceeded, and the TLOV bit of the hardware sequence flag changes to "1".
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It appears to have been written as "1".
However, even if it appears to have been written as "1", the actual data remains "0" and "0" will be read
out when the data is read in read/reset mode. If you want to return data to "1", perform a chip erase or
sector erase.
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During write operations, all commands written to flash memory are ignored.
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If this device is reset during a write, the data that was written cannot be guaranteed.
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Because this series has the ECC bit added, data always needs to be written as 32-bit by two 16-bit writes.
See "5.2 Programming Flash Memory by CPU" for the procedure.
MB91520 Series
MN705-00010-1v0-E
1961