Fujitsu FR81S User Manual
CHAPTER 45: FLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
50
5.9.4. Flash Access Restrictions When Security is ON
Flash access restrictions when security is ON are shown below.
When security is on, the restrictions shown below are created by the start mode.
Table 5-3
Access Restrictions when Security is ON
Operating
mode
Access restriction
User / external
bus
In normal mode (the state where there are no access restrictions due to the
following flash security violations), writing in the security information area (first
nine words of the FLASH memory) is canceled. Moreover, a sector erase
command to sector 0/sector 1 is ignored.
If an instruction fetch is performed to the on-chip bus area, a reset request is
issued by the flash security violation reset source. Accesses to the flash memory
are not accepted thereafter.
The flash memory returns to the normal state by reset.
Other than above
(writer ets.)
Access to flash memory is restricted.
The data from reads is masked and 0xFFFF_FFFF is returned. Write commands
and sector erase commands are ignored.
Chip erase commands are accepted. See "5.9.3
Unlocking Flash Security
".
Furthermore, while the security is ON, when a data read is performed to the security information storage
area (9 words at the start of the flash memory)
⋅
A data access error will occur, and an illegal instruction exception or data access error interrupt will
occur. (See "FR Family FR81 32-bit microcontroller programming manual" and "11.1 MPU control
register (MPUCR) of CHAPTER CPU" for details. )
⋅
0xFFFFFFFF is returned as the read value.
However, when the OCD tool is connected, this restriction does not apply to access from OCDU or read
during the debug state.
MB91520 Series
MN705-00010-1v0-E
1971